The present disclosure relates to semiconductor device fabrication, and more particularly to methods of reducing resist shadowing during ion implantation in forming source/drain regions in fin field effect transistors (FinFETs) for complementary metal oxide semiconductor (CMOS) integration.
FinFETs are one of the leading candidates to replace classical planar metal-oxide-semiconductor field effect transistors (MOSFETs) for future CMOS technologies due to the multiple-gate configuration of the fin device leading to an intrinsically superior short channel effect (SCE) control. Conventionally, source/drain regions in FinFETs are formed by implanting dopants into fins and during the ion implantation, one of the devices types, e.g., n-type FinFETs (nFinFETs), must be covered or masked with a layer of material, such as photoresist, so dopants are implanted only into another device type, e.g., p-type FinFETs (pFinFETs). Scaling of FinFETs creates new challenges for source/drain formation for CMOS integration. After forming the resist layer over the gate, the high topography of the resist layer prevents ions from being implanted into fins close to boundaries of pFinFETs and nFinFETs. This is known as resist shadowing. Therefore, there remains a need to reduce the resist shadowing during ion implantation in forming source/drain regions in FinFETs for CMOS integration.